This relates generally to logic circuits employing shift registers and more particularly to logic circuits which require double clocking latches during testing of the circuits and single clocking latches when the circuits are operating in their non-test or function mode.
Microprocessors, which employ a large number of latching circuits, require both master and slave latching circuits with a plurality of clocks arranged such that the shift registers can be latched during the testing mode, but operated as an unlatched register during the normal or function operation mode. In the prior art this is accomplished by using master and slave circuits coupled in series. Such complex circuits can not use common tests as stuck fault testing.
The present invention is directed toward a register circuit that has, during operation, stable data inputs and thus requires only a single clock to capture and hold the output data, but during testing must act as a shift register latch. In order to prevent race conditions in such shift register latches they require double clocking to scan data into and out of the scan rings formed of the registers.
In particular, the invention described a latching circuit that will operate with a single clocked circuit under one set of selected conditions and under a different set of selected conditions will operate as a dynamic master latch followed by a static slave latch, each set by different clocks. If desired, a third clock, which is optional, can be used to provide the scan features to set internal test points and read internal logic points on the circuit.
The present invention thus provides a simple circuit that will meet the level sensor scan design for automatic generation of stuck fault test while providing a simple circuit which will reduce logic delay.